1. Field of the Invention
The present invention relates to semiconductor devices having element isolation regions, and to techniques for fabricating the semiconductor devices.
2. Description of the Related Art
With recent progress in enhanced performances and multi-functionalization of mobile instruments and personal audio equipments, there are strong needs of reducing power consumption and of enhancing performances of LSIs used for such instruments or equipment. CMOS devices fabricated using bulk substrate are suffering from a problem of increase in power consumption, due to higher degrees of integration and faster operational speed as a result of dimensional shrinkage of semiconductor processes. Accordingly, a CMOS device having a novel structure, operable at low power consumption, is strongly expected. In this situation, semiconductor devices (called “SOI devices”) fabricated by using SOI (Silicon On Insulator or Semiconductor On Insulator) substrates having buried insulating films therein are expected as devices capable of achieving low power consumption and dimensional shrinkage of LSIs. Advantages of the SOI device reside in complete electrical isolation of elements such as PMOS transistor and NMOS transistor, and implementation of high-density layout, without causing latch-up, by virtue of provision of the buried insulating film (e.g., a BOX film).
SOI devices can be classified into partially depleted SOI (PD-SOI) devices and fully depleted SOI (FD-SOI) devices. Both types of the SOI device have a body region surrounded by a gate insulating film, a source diffusion region, a drain diffusion region, and a buried insulating film, directly under a gate electrode. The PD-SOI device has a partially-depleted body region, and suffers for example from degradation of sub-threshold characteristic (i.e., S factor) during operation of the device, due to floating body effect. On the other hand, the FD-SOI device will cause no floating body effect, since the body region is completely depleted, and has an advantage of capable of operating at low voltage and low current consumption.
The element isolation structure can be formed by LOCOS (Local Oxidation Of Silicon) or STI (Shallow Trench Isolation). LOCOS refers to a method of forming an insulating film for element isolation, by thermally oxidizing the surface of the semiconductor substrate, whereas STI refers to a method of forming a shallow trench in the semiconductor substrate, and then filling the trench with an insulating film.
Prior art documents regarding the SOI device and the element isolation techniques are exemplified by Japanese Patent Application Publication Nos. 2003-289144 and H06 (1994)-140427.
Besides the above-described element isolation techniques such as LOCOS and STI, another possible method can be used such as selective etching of the surface of a semiconductor substrate so as to form a mesa-shape semiconductor layer that is used as an active region (element region) (“mesa isolation process”). A transistor structure can be fabricated by forming a gate structure (a gate insulating film and a gate electrode) on the mesa-shape semiconductor layer, and introducing impurities into the semiconductor layer on both sides of the gate structure, to thereby form source/drain diffusion regions. The source/drain diffusion regions are electrically connected through contact plugs to upper interconnects. The contact plugs can be formed typically by selectively etching an insulating interlayer which covers the source/drain diffusion regions to thereby form contact holes, and by filling the contact holes with an electro-conductive material such as tungsten.
When the transistor structure is formed on the SOI substrate by the mesa isolation process, the semiconductor layer in the process of forming the mesa is etched, until the top surface of the buried insulating film in the SOI substrate exposes in the element isolation region, as detailed later. Formation of the transistor structure using the mesa-shape semiconductor layer is followed by a process of depositing an insulating interlayer over the entire surface, and a process of selectively etching the insulating interlayer to thereby form the contact holes which reach the source/drain diffusion regions. The contact holes can, however, occasionally be misaligned, and the region for forming the contact holes can overlap the buried insulating film which exposes in the element isolation region. In this case, element characteristics can degrade if the buried insulating film is excessively etched together with the insulating interlayer in the process of forming the contact holes.
Also in the transistor structure having the element isolation region formed by LOCOS or STI, such misalignment of the contact holes can result in overlapping of the region for forming the contact holes with the element isolation insulating film. Also in this case, the element characteristics possibly degrades if the element isolation insulating film is excessively etched together with the insulating interlayer in the process of forming the contact holes.
In view of the foregoing, it is an object of the present invention to provide a SOI substrate and a method of fabricating the same, and a semiconductor device and a method of fabricating the same which are capable of suppressing degradation of device characteristics, even if misalignment of a contact hole formed in an insulating interlayer over a substrate should occur, thus forming an overlapping region between a contact hole and an element isolation region.